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Memory management unit (MMU)
Hardware that controls caches and access permissions to blocks of memory, and
translates virtual to physical addresses.
Memory Protection Unit (MPU)
Hardware that controls access permissions to blocks of memory. Unlike an MMU, an
MPU does not translate virtual addresses to physical addresses.
RESET
Abbreviation of System Reset. The electronic signal which causes the target system
other than the TAP controller to be reset. This signal is also known as "nSRST"
"nSYSRST", "nRST", or "nRESET" in some other manuals. See also nTRST.
Open collector
A signal that may be actively driven LOW by one or more drivers, and is otherwise
passively pulled HIGH. Also known as a "wired AND" signal.
Processor Core
The part of a microprocessor that reads instructions from memory and executes
them, including the instruction fetch unit, arithmetic and logic unit, and the register
bank. It excludes optional coprocessors, caches, and the memory management unit.
Program Status Register (PSR)
Contains some information about the current program and some information about
the current processor state. Often, therefore, also referred to as Processor Status
Register.
Also referred to as Current PSR (CPSR), to emphasize the distinction to the Saved
PSR (SPSR). The SPSR holds the value of PSR when the current function was called,
and which will be restored when control is returned.
Remapping
Changing the address of physical memory or devices after the application has started
executing. This is typically done to make RAM replace ROM once the initialization has
been done.
RTOS
Real Time Operating System.
Semihosting
A mechanism whereby the target communicates I/O requests made in the application
code to the host system, rather than attempting to support the I/O itself.
Target
The actual processor (real silicon or simulated) on which the application program is
running.
Transistor-transistor logic (TTL)
A type of logic design in which two bipolar transistors drive the logic output to one or
zero. LSI and VLSI logic often used TTL with HIGH logic level approaching +5V and
LOW approaching 0V.
Watchpoint
A location within the image that will be monitored and that will cause execution to
stop when it changes.
J-Link ColdFire BDM 26 (UM08009)
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